[SeaBIOS] [PATCH 4/8] seabios: pciinit: make pci bar assigner preferchable memory aware.

[Isaku Yamahata]

Make pci bar assigner preferchable memory aware.
This is needed for PCI bridge support because memory space and
prefetchable memory space is filtered independently based on
memory base/limit and prefetchable memory base/limit of pci bridge.
On bus 0, such a distinction isn't necessary so keep existing behavior
by checking bus=0.

Signed-off-by: Isaku Yamahata <yamahata at valinux.co.jp>
---
 src/pciinit.c |   10 ++++++++++
 1 files changed, 10 insertions(+), 0 deletions(-)

diff --git a/src/pciinit.c b/src/pciinit.c
index b635e44..b6ab157 100644
--- a/src/pciinit.c
+++ b/src/pciinit.c
@@ -16,6 +16,7 @@
 
 static u32 pci_bios_io_addr;
 static u32 pci_bios_mem_addr;
+static u32 pci_bios_prefmem_addr;
 /* host irqs corresponding to PCI irqs A-D */
 static u8 pci_irqs[4] = {
     10, 10, 11, 11
@@ -70,6 +71,12 @@ static int pci_bios_allocate_region(u16 bdf, int region_num)
         u32 size = (~(val & mask)) + 1;
         if (val & PCI_BASE_ADDRESS_SPACE_IO)
             paddr = &pci_bios_io_addr;
+        else if ((val & PCI_BASE_ADDRESS_MEM_PREFETCH) &&
+                 /* keep behaviour on bus = 0 */
+                 pci_bdf_to_bus(bdf) != 0 &&
+                 /* If pci_bios_prefmem_addr == 0, keep old behaviour */
+                 pci_bios_prefmem_addr != 0)
+            paddr = &pci_bios_prefmem_addr;
         else
             paddr = &pci_bios_mem_addr;
         *paddr = ALIGN(*paddr, size);
@@ -221,6 +228,9 @@ pci_setup(void)
     pci_bios_io_addr = 0xc000;
     pci_bios_mem_addr = BUILD_PCIMEM_START;
 
+    /* pci_bios_mem_addr + <some value> */
+    pci_bios_prefmem_addr = pci_bios_mem_addr + 0x08000000;
+
     int bdf, max;
     foreachpci(bdf, max) {
         pci_bios_init_bridges(bdf);
-- 
1.6.6.1