[SeaBIOS] [PATCH v2 3/6] pci: 64bit support.
Gerd Hoffmann
kraxel at redhat.com
Wed Feb 29 12:45:07 CET 2012
Makes pciinit.c 64bit aware. Use 64bit everywhere. Support discovery
and configuration of 64bit bars, with non-zero upper32 bits. While
being at it introduce a struct pci_bar which can be passed easily.
Signed-off-by: Gerd Hoffmann <kraxel at redhat.com>
---
src/pci.h | 14 ++++--
src/pciinit.c | 126 +++++++++++++++++++++++++++++++++++----------------------
2 files changed, 87 insertions(+), 53 deletions(-)
diff --git a/src/pci.h b/src/pci.h
index a2a5a4c..46f162e 100644
--- a/src/pci.h
+++ b/src/pci.h
@@ -39,6 +39,14 @@ void pci_config_maskw(u16 bdf, u32 addr, u16 off, u16 on);
struct pci_device *pci_find_device(u16 vendid, u16 devid);
struct pci_device *pci_find_class(u16 classid);
+struct pci_bar {
+ u64 addr;
+ u64 size;
+ int is64:1,
+ ismem:1,
+ isprefetch:1;
+};
+
struct pci_device {
u16 bdf;
u8 rootbus;
@@ -51,11 +59,7 @@ struct pci_device {
u8 prog_if, revision;
u8 header_type;
u8 secondary_bus;
- struct {
- u32 addr;
- u32 size;
- int is64;
- } bars[PCI_NUM_REGIONS];
+ struct pci_bar bars[PCI_NUM_REGIONS];
// Local information on device.
int have_driver;
diff --git a/src/pciinit.c b/src/pciinit.c
index 652564c..aa391a0 100644
--- a/src/pciinit.c
+++ b/src/pciinit.c
@@ -35,12 +35,12 @@ struct pci_bus {
struct {
/* pci region stats */
u32 count[32 - PCI_MEM_INDEX_SHIFT];
- u32 sum, max;
+ u64 sum, max;
/* seconday bus region sizes */
- u32 size;
+ u64 size;
/* pci region assignments */
- u32 bases[32 - PCI_MEM_INDEX_SHIFT];
- u32 base;
+ u64 bases[32 - PCI_MEM_INDEX_SHIFT];
+ u64 base;
} r[PCI_REGION_TYPE_COUNT];
struct pci_device *bus_dev;
};
@@ -65,13 +65,13 @@ static u32 pci_index_to_size(int index, enum pci_region_type type)
return 0x1 << (index + shift);
}
-static enum pci_region_type pci_addr_to_type(u32 addr)
+static enum pci_region_type pci_addr_to_type(struct pci_bus *bus, struct pci_bar *bar)
{
- if (addr & PCI_BASE_ADDRESS_SPACE_IO)
+ if (!bar->ismem)
return PCI_REGION_TYPE_IO;
- if (addr & PCI_BASE_ADDRESS_MEM_PREFETCH)
- return PCI_REGION_TYPE_PREFMEM;
- return PCI_REGION_TYPE_MEM;
+ if (!bar->isprefetch)
+ return PCI_REGION_TYPE_MEM;
+ return PCI_REGION_TYPE_PREFMEM;
}
static u32 pci_bar(struct pci_device *pci, int region_num)
@@ -86,9 +86,15 @@ static u32 pci_bar(struct pci_device *pci, int region_num)
}
static void
-pci_set_io_region_addr(struct pci_device *pci, int region_num, u32 addr)
+pci_set_io_region_addr(struct pci_device *pci, int region_num,
+ u64 addr, int is64)
{
- pci_config_writel(pci->bdf, pci_bar(pci, region_num), addr);
+ u32 ofs = pci_bar(pci, region_num);
+
+ pci_config_writel(pci->bdf, ofs, addr & 0xffffffff);
+ if (is64) {
+ pci_config_writel(pci->bdf, ofs + 4, addr >> 32);
+ }
}
@@ -141,10 +147,10 @@ static const struct pci_device_id pci_isa_bridge_tbl[] = {
static void storage_ide_init(struct pci_device *pci, void *arg)
{
/* IDE: we map it as in ISA mode */
- pci_set_io_region_addr(pci, 0, PORT_ATA1_CMD_BASE);
- pci_set_io_region_addr(pci, 1, PORT_ATA1_CTRL_BASE);
- pci_set_io_region_addr(pci, 2, PORT_ATA2_CMD_BASE);
- pci_set_io_region_addr(pci, 3, PORT_ATA2_CTRL_BASE);
+ pci_set_io_region_addr(pci, 0, PORT_ATA1_CMD_BASE, 0);
+ pci_set_io_region_addr(pci, 1, PORT_ATA1_CTRL_BASE, 0);
+ pci_set_io_region_addr(pci, 2, PORT_ATA2_CMD_BASE, 0);
+ pci_set_io_region_addr(pci, 3, PORT_ATA2_CTRL_BASE, 0);
}
/* PIIX3/PIIX4 IDE */
@@ -158,13 +164,13 @@ static void piix_ide_init(struct pci_device *pci, void *arg)
static void pic_ibm_init(struct pci_device *pci, void *arg)
{
/* PIC, IBM, MPIC & MPIC2 */
- pci_set_io_region_addr(pci, 0, 0x80800000 + 0x00040000);
+ pci_set_io_region_addr(pci, 0, 0x80800000 + 0x00040000, 0);
}
static void apple_macio_init(struct pci_device *pci, void *arg)
{
/* macio bridge */
- pci_set_io_region_addr(pci, 0, 0x80800000);
+ pci_set_io_region_addr(pci, 0, 0x80800000, 0);
}
static const struct pci_device_id pci_class_tbl[] = {
@@ -330,14 +336,14 @@ static u32 pci_size_roundup(u32 size)
}
static void
-pci_bios_get_bar(struct pci_device *pci, int bar, u32 *val, u32 *size)
+pci_bios_get_bar(struct pci_device *pci, int nr, struct pci_bar *bar)
{
- u32 ofs = pci_bar(pci, bar);
+ u32 ofs = pci_bar(pci, nr);
u16 bdf = pci->bdf;
u32 old = pci_config_readl(bdf, ofs);
- u32 mask;
+ u64 mask;
- if (bar == PCI_ROM_SLOT) {
+ if (nr == PCI_ROM_SLOT) {
mask = PCI_ROM_ADDRESS_MASK;
pci_config_writel(bdf, ofs, mask);
} else {
@@ -347,12 +353,38 @@ pci_bios_get_bar(struct pci_device *pci, int bar, u32 *val, u32 *size)
mask = PCI_BASE_ADDRESS_MEM_MASK;
pci_config_writel(bdf, ofs, ~0);
}
- *val = pci_config_readl(bdf, ofs);
+ bar->addr = pci_config_readl(bdf, ofs);
pci_config_writel(bdf, ofs, old);
- *size = (~(*val & mask)) + 1;
+ if ((bar->addr & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_MEMORY) {
+ bar->ismem = 1;
+ if ((bar->addr & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
+ PCI_BASE_ADDRESS_MEM_TYPE_64)
+ bar->is64 = 1;
+ if (bar->addr & PCI_BASE_ADDRESS_MEM_PREFETCH)
+ bar->isprefetch = 1;
+ }
+ if (bar->is64) {
+ u32 hold, high;
+ hold = pci_config_readl(bdf, ofs + 4);
+ pci_config_writel(bdf, ofs + 4, ~0);
+ high = pci_config_readl(bdf, ofs + 4);
+ pci_config_writel(bdf, ofs + 4, hold);
+ bar->addr |= ((u64)high << 32);
+ mask |= ((u64)0xffffffff << 32);
+ bar->size = (~(bar->addr & mask)) + 1;
+ } else if (bar->addr != 0) {
+ bar->size = (~(bar->addr & mask) & 0xffffffff) + 1;
+ }
+ if (bar->addr != 0) {
+ dprintf(1, " %d: addr %llx size %llx %s %s%s\n", nr,
+ bar->addr, bar->size,
+ bar->ismem ? "mem" : "io",
+ bar->is64 ? "64bit" : "32bit",
+ bar->isprefetch ? " prefetchable" : "");
+ }
}
-static void pci_bios_bus_reserve(struct pci_bus *bus, int type, u32 size)
+static void pci_bios_bus_reserve(struct pci_bus *bus, int type, u64 size)
{
u32 index;
@@ -384,18 +416,14 @@ static void pci_bios_check_devices(struct pci_bus *busses)
foreachpci(pci) {
if (pci->class == PCI_CLASS_BRIDGE_PCI)
continue;
+ dprintf(1, "PCI: check device bdf=%02x:%02x.%x\n",
+ pci_bdf_to_bus(pci->bdf), pci_bdf_to_dev(pci->bdf),
+ pci_bdf_to_fn(pci->bdf));
for (i = 0; i < PCI_NUM_REGIONS; i++) {
- u32 val, size;
- pci_bios_get_bar(pci, i, &val, &size);
- if (val == 0)
+ pci_bios_get_bar(pci, i, &pci->bars[i]);
+ if (pci->bars[i].addr == 0)
continue;
- pci->bars[i].addr = val;
- pci->bars[i].size = size;
- pci->bars[i].is64 = (!(val & PCI_BASE_ADDRESS_SPACE_IO) &&
- (val & PCI_BASE_ADDRESS_MEM_TYPE_MASK)
- == PCI_BASE_ADDRESS_MEM_TYPE_64);
-
if (pci->bars[i].is64)
i++;
}
@@ -411,7 +439,7 @@ static void pci_bios_check_devices(struct pci_bus *busses)
if (pci->bars[i].addr == 0)
continue;
- type = pci_addr_to_type(pci->bars[i].addr);
+ type = pci_addr_to_type(bus, &pci->bars[i]);
pci_bios_bus_reserve(bus, type,
pci->bars[i].size);
@@ -429,7 +457,7 @@ static void pci_bios_check_devices(struct pci_bus *busses)
struct pci_bus *parent = &busses[pci_bdf_to_bus(s->bus_dev->bdf)];
int type;
for (type = 0; type < PCI_REGION_TYPE_COUNT; type++) {
- u32 limit = (type == PCI_REGION_TYPE_IO) ?
+ u64 limit = (type == PCI_REGION_TYPE_IO) ?
PCI_BRIDGE_IO_MIN : PCI_BRIDGE_MEM_MIN;
s->r[type].size = s->r[type].sum;
if (s->r[type].size < limit)
@@ -437,7 +465,8 @@ static void pci_bios_check_devices(struct pci_bus *busses)
s->r[type].size = pci_size_roundup(s->r[type].size);
pci_bios_bus_reserve(parent, type, s->r[type].size);
}
- dprintf(1, "PCI: secondary bus %d sizes: io %x, mem %x, prefmem %x\n",
+ dprintf(1, "PCI: secondary bus %d sizes: "
+ "io %llx, mem %llx, prefmem %llx\n",
secondary_bus,
s->r[PCI_REGION_TYPE_IO].size,
s->r[PCI_REGION_TYPE_MEM].size,
@@ -474,19 +503,20 @@ static int pci_bios_init_root_regions(struct pci_bus *bus, u32 start, u32 end)
static void pci_bios_init_bus_bases(struct pci_bus *bus)
{
- u32 base, newbase, size;
+ u64 base, newbase, size;
int type, i;
for (type = 0; type < PCI_REGION_TYPE_COUNT; type++) {
- dprintf(1, " type %s max %x sum %x base %x\n", region_type_name[type],
- bus->r[type].max, bus->r[type].sum, bus->r[type].base);
+ dprintf(1, " type %s max %llx sum %llx base %llx\n",
+ region_type_name[type], bus->r[type].max,
+ bus->r[type].sum, bus->r[type].base);
base = bus->r[type].base;
for (i = ARRAY_SIZE(bus->r[type].count)-1; i >= 0; i--) {
size = pci_index_to_size(i, type);
if (!bus->r[type].count[i])
continue;
newbase = base + size * bus->r[type].count[i];
- dprintf(1, " size %8x: %d bar(s), %8x -> %8x\n",
+ dprintf(1, " size %8llx: %d bar(s), %8llx -> %8llx\n",
size, bus->r[type].count[i], base, newbase - 1);
bus->r[type].bases[i] = base;
base = newbase;
@@ -530,8 +560,8 @@ static void pci_bios_map_devices(struct pci_bus *busses)
dprintf(1, "PCI: init bases bus %d (secondary)\n", secondary_bus);
pci_bios_init_bus_bases(s);
- u32 base = s->r[PCI_REGION_TYPE_IO].base;
- u32 limit = base + s->r[PCI_REGION_TYPE_IO].size - 1;
+ u64 base = s->r[PCI_REGION_TYPE_IO].base;
+ u64 limit = base + s->r[PCI_REGION_TYPE_IO].size - 1;
pci_config_writeb(bdf, PCI_IO_BASE, base >> PCI_IO_SHIFT);
pci_config_writew(bdf, PCI_IO_BASE_UPPER16, 0);
pci_config_writeb(bdf, PCI_IO_LIMIT, limit >> PCI_IO_SHIFT);
@@ -564,15 +594,15 @@ static void pci_bios_map_devices(struct pci_bus *busses)
if (pci->bars[i].addr == 0)
continue;
- int type = pci_addr_to_type(pci->bars[i].addr);
- u32 addr = pci_bios_bus_get_addr(bus, type, pci->bars[i].size);
- dprintf(1, " bar %d, addr %x, size %x [%s]\n",
- i, addr, pci->bars[i].size, region_type_name[type]);
- pci_set_io_region_addr(pci, i, addr);
+ int type = pci_addr_to_type(bus, &pci->bars[i]);
+ u64 addr = pci_bios_bus_get_addr(bus, type, pci->bars[i].size);
+ dprintf(1, " bar %d, addr %llx, size %llx [%s]\n",
+ i, addr, pci->bars[i].size,
+ region_type_name[type]);
+ pci_set_io_region_addr(pci, i, addr, pci->bars[i].is64);
if (pci->bars[i].is64) {
i++;
- pci_set_io_region_addr(pci, i, 0);
}
}
}
--
1.7.1
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